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th cv219_rev. 2 . 3 0 _e copyright ? 201 7 thine electronics , inc. thine electronics, inc. security e 1 / 17 thcv2 19 v - by - one? hs high - speed vide o data transmitter general description thcv219 is designed to support video data transmission between the host and display. one high - speed lane can carry up to 32bit data and 3 bits of synchronizing signals a t a pixel clock frequency from 7.5 mhz to 75 mhz. it has one high - speed data lane and, maximum serial data rate is 3.0 gbps/lane. width link ttl clock freq. 24bit si/so 10mhz to 100mhz 32bit si/so 7.5mhz to 75mhz si/so : single - in/single - out, features ? color depth selectable: 24(8*3)/32(10*3)bit ? single link ? ac coupling for high speed lines ? wide range supply voltage 2. 3 ~ 3.6 v ? package: 64 pin qfn ? wide frequency range ? spread spectrum clocking tolerant up to 30 khz/ ? 0. 5% (center spread) ? v - by - one ? hs standard version1.4 compliant ? aec - q100 esd protection block diagram r 9 - r 0 g 9 - g 0 b 9 - b 0 c o n t 2 , c o n t 1 h s y n c v s y n c d e a s y n d e c l k i n c o l l f s e l b e t p d n r f c m l d r v p r e f o r m a t t e r s e r i a l i z e r p l l c o n t r o l s h t p d n l o c k n t x p t x n t h c v 2 1 9 c m o s i n p u t l d o a v c c c a p o u t c a p i n a c a p i n p v c c
th cv219_rev. 2 . 3 0 _e copyright ? 201 7 thine electronics , inc. thine electronics, inc. security e 2 / 17 c o ntents page general description ................................ ................................ ................................ ................................ ................. 1 features ................................ ................................ ................................ ................................ ................................ ... 1 block diagram ................................ ................................ ................................ ................................ ........................ 1 pin c onfiguration ................................ ................................ ................................ ................................ .................... 3 pin description ................................ ................................ ................................ ................................ ........................ 4 functional des cription ................................ ................................ ................................ ................................ ............ 5 absolute maximum ratings* ................................ ................................ ................................ ................................ 10 recommended operating conditions ................................ ................................ ................................ .................... 10 electrical specifications ................................ ................................ ................................ ................................ ........ 10 ac timing diagrams and test circuits ................................ ................................ ................................ ................. 12 input data mapping ................................ ................................ ................................ ................................ ............... 15 package ................................ ................................ ................................ ................................ ................................ .. 16 notices and requests ................................ ................................ ................................ ................................ ............. 17
th cv219_rev. 2 . 3 0 _e copyright ? 201 7 thine electronics , inc. thine electronics, inc. security e 3 / 17 pin c onfiguration test1 pdn cont2 clkin vcc b1 b0 g1 g0 r1 r0 cont1 b3 vcc b2 g3 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 lfsel 49 32 g2 pre 50 31 r3 avcc 51 30 r2 test2 52 29 vcc capout 53 28 de capinp 54 27 vsync capina 55 26 hsync gnd 56 25 b9 txp 57 24 gnd txn 58 (top view) 23 b8 gnd 59 65 expgnd 22 b7 lockn 60 21 b6 htpdn 61 20 b5 bet 62 19 vcc col 63 18 b4 cmldrv 64 17 g9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 asynde rf r4 r5 vcc r6 r7 r8 r9 gnd g4 g5 g6 vcc g7 g8 thcv219
th cv219_rev. 2 . 3 0 _e copyright ? 201 7 thine electronics , inc. thine electronics, inc. security e 4 / 17 pin description pin name pin # type* description r9-r0 9,8,7,6,4, 3,31,30,39,38 i3 pixel data inputs g9-g0 17,16,15,13,12, 11,33,32,41,40 i3 pixel data inputs b9-b0 25,23,22,21,20, 18,36,34,43,42 i3 pixel data inputs cont1,2 37,46 i3 user defined data inputs. active only in 32bit mode. de 28 i3 de input vsync 27 i3 vsync input hsync 26 i3 hsync input clkin 45 i3 pixel clock input txn/p 58,57 co high-speed cml signal output. lockn 60 i3l lock detect input. must be connected to rx lockn with a 10k pull-up resistor. htpdn 61 i3l hot plug detect input. must be connected to rx htpdn with a 10k pull-up resistor. pdn 47 i3l power down input. h: normal operation l: power down pre 50 i3 pre-emphasis level select input. h : pre-emphasis enable l : pre-emphasis disable cmldrv 64 i3 cml outputs drive strength select input. h : normal drive strength l : weak drive strength col** 63 i3 data width setting. h : 24bit l : 32bit lfsel** 49 i3 frequency range setting. h: low frequency operation l: normal operation asynde 1 i3 asynchronous de input. h: normal operation (asynde function disable) l: de input invert operation (asynde function enable) rf 2 i3 input clock triggering edge select input for latching input data h: rising edge l: falling edge bet 62 i3 field-bet entry. h : field bet operation l : normal operation test1 48 - test pin, must be l for normal operation. test2 52 - test pin, must be l for normal operation. capout 53 - decoupling capacitor pins. this pin should be connected to external decoupling capacitors. recommended capacitance is 2.2uf capinp 54 - reference input for pll circuit.must be tied capout. capina 55 - reference input for analog circuit.must be tied capout. vcc 5,14,19,29, 35,44 ps digital power supply pins avcc 51 ps analog power supply pin gnd 10,24,56,59 ps ground pins expgnd 65 ps exposed pad ground *type symbol i3=3.3v cmos input, i3l=low speed 3.3v cmos input co=cml output, ps=power supply **col, lfsel pin col pin and/or lfsel pin level shall not be changed during operation. if ether pin level is changed during operation, pdn shall be toggled (h-> l -> h) after the change.
th cv219_rev. 2 . 3 0 _e copyright ? 201 7 thine electronics , inc. thine electronics, inc. security e 5 / 17 functional description functional overview with v - by - one ? hs proprietary encoding scheme and cdr (clock and data recovery) architecture, thcv21 9 enable s transmission of 8/10 bit rgb, 2bits of user - defined data (cont), synchronizing signals hsync, vsync, and de by a pair cable with minimal external components. thcv 219 inputs cmos/ttl data (including video data, cont, hsync, vsync, and de) and serializes vi deo data and synchronizing signals separately, depending on the polarity of de. de is a signal which indicates whether video or synchronizing data are active. when de is high, it serializes video data inputs into differential data streams. and it transmits serialized synchronizing data when de is low. thcv219 can operate for a wide range of a serial bit rate from 600mbps to 3.0 gbps. it does not need any external frequency reference, such as a crystal oscillator. internal reference output/input function (c apout,capina,capinp) an internal regulator produces the 1.2v (capout). this 1.2v linear regulator can not supply any other external loads. bypass capout to gnd with 2.2uf. capinp supplies reference voltage for int ernal pll, and capina supplies reference vo ltage for any internal analog circuit. bypass capinp/capina to gnd with 0.1uf to remove high frequency noise. capout, capina and capinp must be tied together. analog power supply avcc is supposed to be stabilized with de - coupling capacitor and series noi se filter (for example, ferrite bead). figure 1. connection of capout, capina, capinp and decoupling capacitor c a p o u t c a p i n a c a p i n p t h c v 2 1 9 2 . 2 u f 0 . 1 u f 0 . 1 u f a v c c p o w e r s u p p l y
th cv219_rev. 2 . 3 0 _e copyright ? 201 7 thine electronics , inc. thine electronics, inc. security e 6 / 17 data enable figure 2 is the conceptual diagram of the basic operation of the chipset. THCV220 in figure 2 is a n example of v - by - one ? hs receiver. there are some requirements for de. figure 3 shows the timing diagram of it. figure 2. conceptual diagram of the basic operation of the chipset figure 3. data and synchronizing signals transmission timing diagram table 1. de requirement r / g / b c o n t v , h s y n c c t l 1 d e t h c v 2 2 0 t h c v 2 1 9 r / g / b c o n t v s y n c h s y n c d e = 1 , r / g / b , c o n t d e = 0 , c t l d e = 1 , v , h s y n c = f i x e d d e = 0 , v , h s y n c 0 c t l a r e p a r t i c u l a r a s s i g n e d b i t a m o n g r / g / b , c o n t t h a t c a n c a r r y a r b i t r a r y d a t a d u r i n g d e = 0 p e r i o d . h i g h l o w h i g h v a l i d d a t a v a l i d d a t a i n v a l i d i n v a l i d d e h s y n c v s y n c r g b c o n t t h c v 2 1 9 i n p u t i n v a l i d v a l i d d a t a c l k i n l o w v a l i d d a t a i n v a l i d i n v a l i d v a l i d d a t a l o w h i g h i n v a l i d v a l i d d a t a ( r f = h ) h i g h l o w h i g h v a l i d d a t a v a l i d d a t a k e e p t h e l a s t d a t a o f d e = l p e r i o d d e h s y n c v s y n c r g b c o n t v a l i d d a t a c l k o u t l o w v a l i d d a t a v a l i d d a t a l o w h i g h v a l i d d a t a ( r f = h ) k e e p t h e l a s t d a t a o f d e = l p e r i o d k e e p t h e l a s t d a t a o f d e = l p e r i o d p a r t i c u l a r a s s i g n e d b i t c t l i s t r a n s m i t t e d e x p e c t t h e f i r s t a n d l a s t p i x e l o f b l a n k i n g p e r i o d . o h t e r s a r e l o w f i x e d . t d e h t d e l t d e h t d e l k e e p t h e l a s t d a t a k e e p t h e l a s t d a t a k e e p t h e l a s t d a t a * r e f e r t o t h e d a t a s h e e t o f t h c v 2 2 0 f o r o u t p u t o p e r a t i o n t h c v 2 2 0 o u t p u t * symbol parameter min. typ. max. unit tdeh de=high duration 2ttcip sec tdel de=low duration 2ttcip sec
th cv219_rev. 2 . 3 0 _e copyright ? 201 7 thine electronics , inc. thine electronics, inc. security e 7 / 17 asynde if asynde input is low, de input is inverted before v - by - one ? hs processing. rgb/cont data is transmitted during de input=low. please be careful this inverted de is outputted from v - by - one ? hs receiver, which may cause polarity mismatch against following system requirement. color depth and frequency range select function thcv21 9 support s a variety of data width and frequency range. refer to table 2 for details. col pin and/or lfsel pin level shall not be changed during operation. if ether pin level is changed during operation, pdn shall be toggled (h - > l - > h) after the change. table 2. operation mode select col lfsel description freq. range l l 32bit 15 to 75m h 32bit low frequency mode 7.5 to 30m h l 24bit 20 to 100m h 24bit low frequency mode 10 to 40m hot - plug function htpdn indicates connecting condition between the transmitter and the receiver. ht pdn of the transmitter side is h igh when the receiver is not active or not connected. then transmitter can enter into the power down mode. htpdn is set to low by the receiver when receiver is active and connects to the transmitter, and then transmitter must start up and transmit cdr training pattern for link training. htpdn is open drain output at the receiver side. pull - up resistor is needed at the transmitter side. htpdn connection between the transmitter and the receiver can be omitted as an application option. in this case, htpdn at the transmitter side should always be taken as low. lock detect function lockn indicates whether the cdr pll is in the lock state or not. lockn at the transmitter input is set to high by pull - up resistor when receiver is not active or at the cdr pll training state. lockn is set to low by the receiver when cdr lock is done. then the cdr training mode finishes and transmitter shifts to the normal mode. lockn is open drain output at the receiver side. pull - up res istor is needed at the transmitter side. when htpdn is included in an application, the lockn signal should only be considered when the htpdn is pulled low by the receiver. figure 4. hot - plug and lock detect scheme v c c ( t x s i d e ) h t p d n l o c k n t h c v 2 1 9 1 0 k h t p d n l o c k n 1 0 k v c c ( t x s i d e ) h t p d n l o c k n t h c v 2 1 9 h t p d n l o c k n v - b y - o n e ? h s r x 1 0 k w i t h h t p d n c o n n e c t w i t h o u t h t p d n c o n n e c t v - b y - o n e ? h s r x
th cv219_rev. 2 . 3 0 _e copyright ? 201 7 thine electronics , inc. thine electronics, inc. security e 8 / 17 pre - emphasis and drive select function pre - emphasis can equalize severe signal degradation caused by long - distance or high - speed transmission. the pre pin selects the strength of pre - emphasis. cml drv controls cml output swing level. see table 3 . table 3. pre - emphasis and drive select function table pre cmldrv description swing level pre - emphasis l l figure 5. 400mv diff p - p figure 6. 0db h 600mv diff p - p h l 400mv diff p - p 6db h 600mv diff p - p 3.5db power down function setting the pdn pin low places thcv219 in the power - down mode. i nternal circuitry turns off and the tx p / n outputs tu rn to high level . table 4. power down function table pdn description l power down h normal operation
th cv219_rev. 2 . 3 0 _e copyright ? 201 7 thine electronics , inc. thine electronics, inc. security e 9 / 17 field bet operation in order to help users to check valid ity of cml high - speed serial line , thcv219 has an operation mode in which they act as a bit error tester (bet). in this mode, thcv219 internally generates test pattern which is then serialized onto the cml high - speed line . THCV220 which is an example or rx device also has bet function mode. thcv22 0 receives the data stream and checks bit errors. this "field bet" mode is activated by setting bet= h both on thcv219 and THCV220 . the generated data pattern is then 8b/10b encoded, scrambled, and serialized onto the cml channel. as for THCV220 , the int ernal test pattern check circuit gets enab led and reports result on a certain pin named betout . th e betout pin goes low whenever bit errors occur, or it stays high when there is no bit error. please refer to table 5 . table 5. field bet operation pin settings thcv219 THCV220 condition bet bet l l normal operation h h field bet operation table 6. THCV220 field bet result betout output l bit error occurred h no error figure 7. field bet configuration t h c v 2 1 9 t h c v 2 2 0 c l k i n b e t = h b e t = h t e s t p a t t e r n c h e c k e r t e s t p a t t e r n g e n e r a t o r t t l d a t a i n p u t s a r e i g n o r e d b e t o u t t e s t p o i n t f o r f i e l d b e t
th cv219_rev. 2 . 3 0 _e copyright ? 201 7 thine electronics , inc. thine electronics, inc. security e 10 / 17 absolute maximum ratings* ? absolute maximum ratings are those values beyond which the safety of the device can not be guaranteed. they are not meant to imply that the device should be operated at these limits. the tables of electrical characteristics specify conditions for device operation. recommended operating conditions electrical specifications cmos dc specifications min. typ. max. unit -0.3 - +4.0 v -0.3 - vcc+0.3 v -0.3 - capina+0.3 v -30 - 30 ma -55 - +125 - - +125 - - +260/10sec - - 3.9 w storage temperature output current parameter supply voltage(vcc,avcc) cmos input voltage cml transmitter output voltage reflow peak temperature/time junction temperature maximum power dissipation @+25 min. typ. max. unit 2.3 2.5 2.7 v 2.6 2.8 3.0 v 3.0 3.3 3.6 v -40 85 parameter operating temperature supply voltage vcc,avcc over recommended operating supply and temperature ranges unless otherwise specified. symbol parameter conditions min. typ. max. unit iih input leak current high -10 +10 ua iil input leak current low -10 +10 ua vcapout regulator output voltage 1.20 v vcc=3.30.3v symbol parameter conditions min. typ. max. unit i3 2.0 vcc v i3l 2.1 vcc v i3 0 0.8 v i3l 0 0.7 v vcc=2.80.2v symbol parameter conditions min. typ. max. unit i3 1.8 vcc v i3l 1.9 vcc v i3 0 0.7 v i3l 0 0.6 v vcc=2.50.2v symbol parameter conditions min. typ. max. unit i3 1.7 vcc v i3l 1.6 vcc v i3 0 0.7 v i3l 0 0.5 v vih high level input voltage vil low level input voltage vih high level input voltage vil low level input voltage vih high level input voltage vil low level input voltage
th cv219_rev. 2 . 3 0 _e copyright ? 201 7 thine electronics , inc. thine electronics, inc. security e 11 / 17 cml dc specifications supply currents switching characteristics over recommended operating supply and temperature ranges unless otherwise specified. symbol parameter conditions min. typ. max. unit cmldrv=l 133 200 267 mv cmldrv=h 200 300 400 mv pre=l 0 % pre=h, cmldrv=l 100 % pre=h, cmldrv=h 50 % pre=l v pre=h, cmldrv=l v pre=h, cmldrv=h v itoh cml output leak current high pdn=l, txp/n=1.2v 30 ua itos cml output short circuit current pdn=l, txp/n=0v -80 ma 1.2 - 2 * vtod pre cml pre-emphasis level 1.2 - vtod vtod cml differential mode output voltage 1.2 - 1.5 * vtod vtoc cml common mode output voltage over recommended operating supply and temperature ranges unless otherwise specified. symbol parameter conditions min. typ. max. unit itccw transmitter supply current col=l pre=h 100 ma itccs transmitter power down supply current pdn=l all inputs =fixed lorh 1.2 10 ma over recommended operating supply and temperature ranges unless otherwise specified. symbol parameter conditions min. typ. max. unit ttrf cml output rise and fall time(20%-80%) 50 150 ps col=h, lfsel=l 10 50 ns col=h, lfsel=h 25 100 ns col=l, lfsel=l 13.34 66.66 ns col=l, lfsel=h 33.34 133.33 ns ttch clk in high time 0.35ttcip 0.5ttcip 0.65ttcip ns ttcl clk in low time 0.35ttcip 0.5ttcip 0.65ttcip ns tts ttl data setup to clk in 2.0 ns tth ttl data hold to clk in 0.6 ns col=h typ. - ttcip 10.6ttcip+1.7 typ. + ttcip ns col=l typ. - ttcip 9.8ttcip+1.7 typ. + ttcip ns ttpd power on to pdn high delay 0 ns ttpll0 pdn high to cml output delay 10 ms ttpll1 pdn low to cml output high fix delay 20 ns ttnp0 lockn high to training pattern output delay 10 ms ttnp1 lockn low to data pattern output delay 10 ms ttcip clkin period input clock to output data delay ttcd
th cv219_rev. 2 . 3 0 _e copyright ? 201 7 thine electronics , inc. thine electronics, inc. security e 12 / 17 ac timing diagrams and test circuits cmos/ttl input switching characteristics figure 8. cmos/ttl input switching timing diagrams cml output switching characteristics figure 9. cml buffer switching timing diagrams and test circuit t t s t t h t t c h ( r f = h ) t t c l ( r f = l ) t t c i p r f = l r f = h v c c / 2 v c c / 2 v c c / 2 c l k i n r 9 - 0 , g 9 - 0 , b 9 - 0 c o n t 1 , c o n t 2 h s y n c , v s y n c d e , a s y n d e v c c / 2 v c c / 2 t t c h ( r f = l ) t t c l ( r f = h ) t x p t x n 7 5 2 0 0 n f < 5 m m v d i f f = ( t x p ) - ( t x n ) 5 0 o h m 5 0 o h m 7 5 2 0 0 n f 2 0 % 8 0 % 2 0 % 8 0 % t t r f t t r f
th cv219_rev. 2 . 3 0 _e copyright ? 201 7 thine electronics , inc. thine electronics, inc. security e 13 / 17 figure 10. cml buffer scheme t x p r x p t x n r x n v b i a s z d i f f = 1 0 0 o h m c = 7 5 2 0 0 n f 5 0 o h m g n d t h c v 2 1 9 v - b y - o n e ? h s r x c m l t r a n s m i t t e r c m l r e c e i v e r 5 0 o h m c a p c = 7 5 2 0 0 n f
th cv219_rev. 2 . 3 0 _e copyright ? 201 7 thine electronics , inc. thine electronics, inc. security e 14 / 17 latency characteristics figure 11. thcv219 latency data output sequence figure 12. thcv219 sequence v d i f f = ( t x p ) - ( t x n ) p i x e l 1 s t b i t r / f = l r / f = h v c c / 2 v c c / 2 v c c / 2 c l k i n t t c i p r 9 - 0 , g 9 - 0 , b 9 - 0 c o n t 1 , c o n t 2 h s y n c , v s y n c d e , a s y n d e t t c d v c c c l k i n h t p d n p d n l o c k n f i x t o c a p i n a t x p / n r g b , c o n t h , v s y n c , d e t r a i n i n g p a t t e r n n o r m a l p a t t e r n t r a i n i n g p a t t e r n d a t a p a t t e r n t t p d t t p l l 0 t t n p 1 t t n p 0 t t p l l 1
th cv219_rev. 2 . 3 0 _e copyright ? 201 7 thine electronics , inc. thine electronics, inc. security e 15 / 17 input data mapping table 7. cmos/ttl inpu t data mapping *1 ctl bits, which are carried during de=low except the 1 st and the last pixel. 10bit (30bpp) 8bit (24bpp) 10bit (30bpp) 8bit (24bpp) r0 *1 - r0 - d30 r1 *1 - r1 - d31 r2 r0 r2 r2 d0 r3 r1 r3 r3 d1 r4 r2 r4 r4 d2 r5 r3 r5 r5 d3 r6 r4 r6 r6 d4 r7 r5 r7 r7 d5 r8 r6 r8 r8 d6 r9 r7 r9 r9 d7 g0 *1 - g0 - d28 g1 *1 - g1 - d29 g2 g0 g2 g2 d8 g3 g1 g3 g3 d9 g4 g2 g4 g4 d10 g5 g3 g5 g5 d11 g6 g4 g6 g6 d12 g7 g5 g7 g7 d13 g8 g6 g8 g8 d14 g9 g7 g9 g9 d15 b0 *1 - b0 - d26 b1 *1 - b1 - d27 b2 *1 b0 *1 b2 b2 d16 b3 *1 b1 *1 b3 b3 d17 b4 *1 b2 *1 b4 b4 d18 b5 *1 b3 *1 b5 b5 d19 b6 *1 b4 *1 b6 b6 d20 b7 *1 b5 *1 b7 b7 d21 b8 *1 b6 *1 b8 b8 d22 b9 *1 b7 *1 b9 b9 d23 cont1 *1 - cont1 - d25 cont2 *1 - cont2 - d24 hsync hsync hsync hsync hsync vsync vsync vsync vsync vsync de de de de de data signals transmitter input pin name symbol defined by v-by-one? hs
th cv219_rev. 2 . 3 0 _e copyright ? 201 7 thine electronics , inc. thine electronics, inc. security e 16 / 17 package l a s e r m a r k f o r p i n 1 9 . 0 0 . 6 5 0 . 9 m a x t o p v i e w 9 . 0 b o t t o m v i e w 6 . 0 0 6 . 0 0 1 . 1 0 0 . 4 5 1 . 1 0 0 . 5 0 . 2 5 0 . 4 1 1 6 1 7 3 2 3 3 4 8 4 9 6 4 p i n 1 i d 0 . 2 0 r 0 . 0 9 r s i d e v i e w
th cv219_rev. 2 . 3 0 _e copyright ? 201 7 thine electronics , inc. thine electronics, inc. security e 17 / 17 notices and requests 1. the product specifications described in this material are subject to change without prior notice. 2. the circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. we are not responsible for possible errors and omissions in this mater ial. please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. this material contains our copyright, know - how or other proprietary. copying or disclosing to third parties the contents of this mater ial without our prior permission is prohibited. 4. note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or func tions of the product. 5. product application 5.1 application of this product is intended for and limited to the following applications: audio - video device, office automation device, communication device, consumer electronics, smartphone, feature phone , and amusement machine device. this product must not be used for applications that require extremely high - reliability/safety such as aerospace device, traffic device, transportation device, nuclear power control device, combustion chamber device, medical de vice related to critical care, or any kind of safety device. 5.2 this product is not intended to be used as an automotive part, unless the product is specified as a product conforming to the demands and specifications of iso/ts16949 ("the specified produc t") in this data sheet. thine electronics, inc. (thine) accepts no liability whatsoever for any product other than the specified product for it not conforming to the aforementioned demands and specifications. 5.3 thine accepts liability for demands and specifications of the specified product only to the extent that the user and thine have been previously and explicitly agreed to each other. 6. despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi - conductor product. therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. p lease note that this product is not designed to be radiation - proof. 8. testing and other quality control techniques are used to this product to the extent thine deems necessary to support warranty for performance of this product . except where mandated by appl icable law or deemed necessary by thine based on the user s request, testing of all functions and performance of the product is not necessarily performed. 9. customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the foreign exchange and foreign trade control law. 10. the product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if pins of the product are shorted by such as foreign substance . the damage may cause a smoking and ignition. therefore, you are encouraged to implement safety measures by adding protection devices, such as fuses. thine electronics, inc. sales@thine.co.jp http://www.thine.co.jp

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